Implementation and testing of high-speed CMOS true random number generators based on chaotic systems

We present the design and the validation by means of suitably improved randomness tests of two different implementations of high-performance true-random number generators which use a discrete-time chaotic circuit as their entropy source. The proposed system has been developed from a standard pipeline Analog-to-Digital converter (ADC) design, modified to operate as a set of piecewise-linear chaotic maps. The evolution of each map is observed and quantized to obtain a random bit stream. With this approach it is possible to obtain, on current CMOS technology, a data rate in the order of tens of megabit per second. Furthermore, we can also prove that the design is tamper resistant in the sense that a power analysis cannot leak information regarding the generated bits. This makes the proposed circuit perfectly suitable for embedding in cryptographic systems like smarts cards, even more so if one consider that it could be easily obtained by reconfiguring an existing pipeline ADC. The two prototypes have been designed in a 0.35 um and 0.18 um CMOS technology, and have a throughput of, respectively, 40 Mbit/s and 100 Mbit/s. A comparison between measured results and other high-end commercial solutions shows a comparable quality with a operating speed that is one order of magnitude faster.