The adoption of multi- and many-core processors in avionic applications is still limited by certification concerns, mainly due to non-deterministic behavior. In this paper, we review requirements of avionic applications, and we identify some of the critical issues that they are going to face on many-core processors. We then propose a preliminary version of a network-on-chip architecture suitable for airworthiness certification, which combines quality-of-service and fault-tolerance.

Deterministic Network On Chip for Deploying Real Time Applications on Many-core Processors / Esposito, Stefano; Violante, Massimo. - ELETTRONICO. - (2017), pp. 21-24. ((Intervento presentato al convegno 2017 IEEE 23rd International Symposium on On-Line Testing and Robust Systems Design tenutosi a Salonicco (GR) nel 3-5 Luglio 2017 [10.1109/IOLTS.2017.8046172].

Deterministic Network On Chip for Deploying Real Time Applications on Many-core Processors

ESPOSITO, STEFANO;VIOLANTE, MASSIMO
2017

Abstract

The adoption of multi- and many-core processors in avionic applications is still limited by certification concerns, mainly due to non-deterministic behavior. In this paper, we review requirements of avionic applications, and we identify some of the critical issues that they are going to face on many-core processors. We then propose a preliminary version of a network-on-chip architecture suitable for airworthiness certification, which combines quality-of-service and fault-tolerance.
978-1-5386-0352-9
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2680498
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