Archivio Istituzionale della RicercaIn this paper we present our final results on the real-time implementation on an FPGA platform of the digital signal processing required in the FDMA-PON architecture studied in the EU project "FABULOUS". For the first time, we demonstrated simultaneous upstream and downstream realtime transmission capable of carrying Gigabit Ethernet bidirectional traffic to each ONU.
Final results from EU project "FABULOUS" / Straullu, S.; Savio, P.; Nespola, A.; Abrate, S.; Ferrero, Valter; Gaudino, Roberto. - ELETTRONICO. - 2016:(2016), pp. 1-4. (Intervento presentato al convegno 18th Italian National Conference on Photonic Technologies, Fotonica 2016 tenutosi a Rome (Italy) nel 2016) [10.1049/cp.2016.0864].
Final results from EU project "FABULOUS"
FERRERO, Valter;GAUDINO, ROBERTO
2016
Abstract
In this paper we present our final results on the real-time implementation on an FPGA platform of the digital signal processing required in the FDMA-PON architecture studied in the EU project "FABULOUS". For the first time, we demonstrated simultaneous upstream and downstream realtime transmission capable of carrying Gigabit Ethernet bidirectional traffic to each ONU.
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https://hdl.handle.net/11583/2671519
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