This paper proposes a new design methodology enabling the co-design of MEMS with electronics while considering the influences of its surrounding package. The proposed solution has been validated on a case study of a MEMS accelerometer. We describe different options to simulate the MEMS accelerometer device with its package. Firstly, as a parametric MEMS+ component model based on high-order finite elements. Secondly, as an automatically generated reduced-order model in VerilogA format. Both models are fully compatible with standard electronic circuit simulators. The comparison between both models reveals that the VerilogA model shows similar accuracy (difference is smaller than 1%) while it is considerably faster in simulation time (by more than a factor of 1000). The proposed methodology can efficiently simulate the interaction between MEMS chip, package and electronic read-out circuit, which is an important part of a new approach of smart system design.
New design methodology for MEMS-electronic-package co-design and validation for inertial sensor systems / Sanginario, Alessandro; Mehdaoui, Alexandre; Zerbini, Sarah; Schropfer, Gerold; Demarchi, Danilo. - ELETTRONICO. - (2015), pp. 1-6. (Intervento presentato al convegno 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 tenutosi a fra nel 27-30 April 2015) [10.1109/DTIP.2015.7160975].
New design methodology for MEMS-electronic-package co-design and validation for inertial sensor systems
Sanginario, Alessandro;DEMARCHI, DANILO
2015
Abstract
This paper proposes a new design methodology enabling the co-design of MEMS with electronics while considering the influences of its surrounding package. The proposed solution has been validated on a case study of a MEMS accelerometer. We describe different options to simulate the MEMS accelerometer device with its package. Firstly, as a parametric MEMS+ component model based on high-order finite elements. Secondly, as an automatically generated reduced-order model in VerilogA format. Both models are fully compatible with standard electronic circuit simulators. The comparison between both models reveals that the VerilogA model shows similar accuracy (difference is smaller than 1%) while it is considerably faster in simulation time (by more than a factor of 1000). The proposed methodology can efficiently simulate the interaction between MEMS chip, package and electronic read-out circuit, which is an important part of a new approach of smart system design.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2646251
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