Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power Hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by protecting their combinational logic parts. The architecture can handle a broad spectrum of faults with little impact on performance by combining different types of redundancies. Moreover, it addresses the problem of error propagation behavior of nonlinear pipelines and error detection in pipeline stages with memory interfaces. Our case-study implementation of fault tolerant MIPS microprocessors highlights four main advantages of the proposed solution. It offers (i) 11.6% power saving, (ii) improved transient error detection capability, (iii) lifetime reliability improvement, and (iv) better fault accumulation effect handling, in comparison with TMR architectures. We also present a gate-level fault-injection framework that offers high fidelity to model physical defects and transient faults.
|Titolo:||A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores|
|Data di pubblicazione:||2016|
|Digital Object Identifier (DOI):||10.1007/s10836-016-5578-0|
|Appare nelle tipologie:||1.1 Articolo in rivista|