This paper proposes a testing method for the evaluation of the inverter dead-time voltage error and the related compensation schemes using a hardware-in-the loop converter topology. The inverter under test is operated as a voltage source that is connected with another twin inverter acting as a virtual load. The virtual load is operated as a current-controlled voltage source converter that draws specified currents having a desired amplitude and phase displacement respect to the voltages generated by the inverter under test. The two converters share the same DC link, so the power required for the test must cover only the total converter losses. This testing approach allows a complete analysis and assessment of dead-time compensation schemes for any operating conditions, such as modulation index, current value and power factor.

Assessment Method of Dead-Time Compensation Schemes of Three-Phase Inverters using a Hardware-In-The-Loop Configuration / Bojoi, IUSTIN RADU; Armando, Eric Giacomo; Mariut, Felix; Odhano, SHAFIQ AHMED. - ELETTRONICO. - (2015), pp. 4097-4104. ((Intervento presentato al convegno IEEE Energy Conversion Congress and Exposition (ECCE-2015) tenutosi a Montreal (Canada) nel 20-24 September, 2015 [10.1109/ECCE.2015.7310238].

Assessment Method of Dead-Time Compensation Schemes of Three-Phase Inverters using a Hardware-In-The-Loop Configuration

BOJOI, IUSTIN RADU;ARMANDO, Eric Giacomo;MARIUT, FELIX;ODHANO, SHAFIQ AHMED
2015

Abstract

This paper proposes a testing method for the evaluation of the inverter dead-time voltage error and the related compensation schemes using a hardware-in-the loop converter topology. The inverter under test is operated as a voltage source that is connected with another twin inverter acting as a virtual load. The virtual load is operated as a current-controlled voltage source converter that draws specified currents having a desired amplitude and phase displacement respect to the voltages generated by the inverter under test. The two converters share the same DC link, so the power required for the test must cover only the total converter losses. This testing approach allows a complete analysis and assessment of dead-time compensation schemes for any operating conditions, such as modulation index, current value and power factor.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2628996
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo