This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.

3DV — An embedded, dense stereovision-based depth mapping system / Camellini, G.; Felisa, M.; Medici, P.; Zani, P.; Gregoretti, Francesco; Passerone, Claudio; Passerone, R.. - (2014), pp. 1435-1440. ((Intervento presentato al convegno Intelligent Vehicles Symposium Proceedings tenutosi a Dearborn, MI; USA nel 8-11 June 2014 [10.1109/IVS.2014.6856563].

3DV — An embedded, dense stereovision-based depth mapping system

GREGORETTI, Francesco;PASSERONE, Claudio;
2014

Abstract

This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2592357
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