Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, tailored to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is wasted due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches with different queueing architectures (one queue per input and one queue for input-output pairs) and show that, despite their simplicity, their performance is comparable or even better than those of synchronous switches. We highlight the peculiar role of the variation coefficient of the packet length. Finally, for synchronous switches we evaluate the actual bandwidth overhead due to packet segmentation, by considering a large set of traffic traces covering the period 2008-2013. We show that an impressive amount of bandwidth (up to 30%) can be lost due to segmentation, even if the internal cell size is optimally chosen. These results demonstrate the potential interest of the asynchronous approach in the design of high-performance switches.

Asynchronous vs Synchronous Input-Queued Switches / Bianco, Andrea; Cuda, Davide; Giaccone, Paolo. - In: COMPUTER COMMUNICATIONS. - ISSN 0140-3664. - STAMPA. - 53:(2014), pp. 52-61. [10.1016/j.comcom.2014.07.007]

Asynchronous vs Synchronous Input-Queued Switches

BIANCO, ANDREA;CUDA, DAVIDE;GIACCONE, PAOLO
2014

Abstract

Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, tailored to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is wasted due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches with different queueing architectures (one queue per input and one queue for input-output pairs) and show that, despite their simplicity, their performance is comparable or even better than those of synchronous switches. We highlight the peculiar role of the variation coefficient of the packet length. Finally, for synchronous switches we evaluate the actual bandwidth overhead due to packet segmentation, by considering a large set of traffic traces covering the period 2008-2013. We show that an impressive amount of bandwidth (up to 30%) can be lost due to segmentation, even if the internal cell size is optimally chosen. These results demonstrate the potential interest of the asynchronous approach in the design of high-performance switches.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2556158
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