Archivio Istituzionale della RicercaDesign and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency.
13-bit GaAs serial-to-parallel converter with compact layout for core-chip applications / Pirola, Marco; Quaglia, Roberto; Ghione, Giovanni; Walter, Ciccognani; Ernesto, Limiti. - In: MICROELECTRONICS JOURNAL. - ISSN 0959-8324. - STAMPA. - 45:7(2014), pp. 864-869. [10.1016/j.mejo.2014.04.036]
13-bit GaAs serial-to-parallel converter with compact layout for core-chip applications
PIROLA, Marco;QUAGLIA, ROBERTO;GHIONE, GIOVANNI;
2014
Abstract
Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency.
| File | Dimensione | Formato | |
|---|---|---|---|
|
Pirolaetal_MicroelectronicsJournal_PROMIX_Major_v0.pdf
Open Access dal 23/05/2016
Tipologia:
2. Post-print / Author's Accepted Manuscript
Licenza:
Creative commons
Dimensione
3.54 MB
Formato
Adobe PDF
|
3.54 MB | Adobe PDF | Visualizza/Apri |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/2545737
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo