Modern embedded systems require a tight integration among several heterogeneous components including both digital and analog HW, as well as HW-dependent SW. Moreover, they have a strict interaction with the surrounding physical environment. Traditional approaches for modeling such systems rely either on homogeneous top-down methodologies or on co-simulation frameworks. The former are generally based on a single model of computation. Thus, they do not easily allow to integrate existing components built by using different formalisms. The latter assemble heterogeneous components without providing a rigorous formal support, thus making integration and validation a very hard tasks. This paper proposes UNIVERCM, a formal computational model that allows to represent with a uniform syntax and a precise semantics heterogeneous systems composed of SW, analog and digital HW, as well as the environment they are embedded in. UNIVERCM is not intended to be explicitly used to describe a system, but rather to automatically convert into a uniform representation different descriptions written by using heterogeneous modeling languages.

UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design / Di Guglielmo, L.; Fummi, F.; Pravadelli, G.; Stefanni, F.; Vinco, Sara. - (2011), pp. 33-40. (Intervento presentato al convegno IEEE International High Level Design Validation and Test Workshop (HLDVT) tenutosi a Napa Valley, CA, USA nel November 9-11, 2011) [10.1109/HLDVT.2011.6114163].

UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design

VINCO, SARA
2011

Abstract

Modern embedded systems require a tight integration among several heterogeneous components including both digital and analog HW, as well as HW-dependent SW. Moreover, they have a strict interaction with the surrounding physical environment. Traditional approaches for modeling such systems rely either on homogeneous top-down methodologies or on co-simulation frameworks. The former are generally based on a single model of computation. Thus, they do not easily allow to integrate existing components built by using different formalisms. The latter assemble heterogeneous components without providing a rigorous formal support, thus making integration and validation a very hard tasks. This paper proposes UNIVERCM, a formal computational model that allows to represent with a uniform syntax and a precise semantics heterogeneous systems composed of SW, analog and digital HW, as well as the environment they are embedded in. UNIVERCM is not intended to be explicitly used to describe a system, but rather to automatically convert into a uniform representation different descriptions written by using heterogeneous modeling languages.
2011
9781457717444
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2529489
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