Enabling Design and Simulation of Massive Parallel Nanoarchitectures

A common element in emerging nanotechnologies is the increasing complex- ity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evalu- ated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architec- tures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotech- nologies, here discussed in the specific case of nanowire arrays, as best candi- date for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDL), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simu- lation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Re- sults about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented.