This approach as effective solution to overcome challenges related to the nanomaterial assembly with electrodes, the low-noise measurement of nanomaterial electrical properties and the CMOS design of the nanosensor electronic interface. This paper presents both the fabrication process of a nanodevice onto the IC surface using Dielectrophoresis (DEP) and the Read- Out Circuit (ROC) used for the inspection of the electrical properties of nanowires (NW). The ROC includes a Time-over- Threshold circuit which has been characterized stand-alone. It shows maximum measurement error of 0.8% with a maximum linearity error below 1.86% in the range 300kΩ-100MΩ. The ROC occupies 0.0067 mm2 silicon area and simulation data shows that the maximum power consumption is 8.9μW at 1.2V. The paper presents first measurement results obtained on fabricated prototype chips based on ZnO-NW.

A Low-Power Read-Out Circuit and Low-Cost Assembly of Nanosensors onto a 0.13 μm CMOS Micro-for-Nano Chip / Bonanno, Alberto; Cauda, Valentina Alice; Crepaldi, Marco; MOTTO ROS, Paolo; Morello, Marco; Demarchi, Danilo; Civera, Pierluigi. - ELETTRONICO. - (2013). ((Intervento presentato al convegno IWASI 2013 tenutosi a Bari, Italy nel June 2013 [10.1109/IWASI.2013.6576056].

A Low-Power Read-Out Circuit and Low-Cost Assembly of Nanosensors onto a 0.13 μm CMOS Micro-for-Nano Chip

BONANNO, ALBERTO;CAUDA, Valentina Alice;CREPALDI, MARCO;MOTTO ROS, PAOLO;MORELLO, MARCO;DEMARCHI, DANILO;CIVERA, PIERLUIGI
2013

Abstract

This approach as effective solution to overcome challenges related to the nanomaterial assembly with electrodes, the low-noise measurement of nanomaterial electrical properties and the CMOS design of the nanosensor electronic interface. This paper presents both the fabrication process of a nanodevice onto the IC surface using Dielectrophoresis (DEP) and the Read- Out Circuit (ROC) used for the inspection of the electrical properties of nanowires (NW). The ROC includes a Time-over- Threshold circuit which has been characterized stand-alone. It shows maximum measurement error of 0.8% with a maximum linearity error below 1.86% in the range 300kΩ-100MΩ. The ROC occupies 0.0067 mm2 silicon area and simulation data shows that the maximum power consumption is 8.9μW at 1.2V. The paper presents first measurement results obtained on fabricated prototype chips based on ZnO-NW.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2508094
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