Archivio Istituzionale della RicercaIn this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification
Algorithm validation and hardware design interactive approach / Lazarescu, MIHAI TEODOR; Sartori, M.. - ELETTRONICO. - 1:(1996), pp. 291-294. (Intervento presentato al convegno International Semiconductor Conference tenutosi a Sinaia, Romania nel October 1996) [10.1109/SMICND.1996.557380].
Algorithm validation and hardware design interactive approach
LAZARESCU, MIHAI TEODOR;
1996
Abstract
In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification
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https://hdl.handle.net/11583/2507491