Biosequence alignment recently received an amazing support from both commodity and dedicated hardware platforms. The limitless requirements of this application motivate the search for improved implementations to boost processing time and capabilities. We propose an unprecedented hardware improvement to the classic Smith-Waterman (S-W) algorithm based on a twofold approach: i) an on-the-fly gap-open/gap-extension selection that reduces the hardware implementation complexity; ii) a pre-selection filter that uses reduced amino-acid alphabets to screen out not-significant sequences and to shorten the S-Witerations on huge reference databases.We demonstrated the improvements w.r.t. a classic approach both from the point of view of algorithm efficiency and of HW performance (FPGA and ASIC post-synthesis analysis).
Protein alignment HW/SW optimizations / Urgese, Gianvito; Graziano, Mariagrazia; Vacca, Marco; Awais, Muhammad; Frache, Stefano; Zamboni, Maurizio. - STAMPA. - (2012), pp. 145-148. (Intervento presentato al convegno Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on tenutosi a Seville, Spain nel 2012) [10.1109/ICECS.2012.6463779].
Protein alignment HW/SW optimizations
URGESE, GIANVITO;GRAZIANO, MARIAGRAZIA;VACCA, MARCO;AWAIS, MUHAMMAD;FRACHE, STEFANO;ZAMBONI, Maurizio
2012
Abstract
Biosequence alignment recently received an amazing support from both commodity and dedicated hardware platforms. The limitless requirements of this application motivate the search for improved implementations to boost processing time and capabilities. We propose an unprecedented hardware improvement to the classic Smith-Waterman (S-W) algorithm based on a twofold approach: i) an on-the-fly gap-open/gap-extension selection that reduces the hardware implementation complexity; ii) a pre-selection filter that uses reduced amino-acid alphabets to screen out not-significant sequences and to shorten the S-Witerations on huge reference databases.We demonstrated the improvements w.r.t. a classic approach both from the point of view of algorithm efficiency and of HW performance (FPGA and ASIC post-synthesis analysis).File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2506470
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