Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but yet a costly one as far as power consumption is concerned. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. In its typical, bulky incarnation with voltage regulators and PLLs or DLLs for frequency synthesis, though, it does not fit very well the need for individual regulation at the level of NoC’s single switch. We propose a simple DVFS mechanism for a NoC switch. It uses just two voltages, high and low, for voltage scaling. For effective frequency scaling a periodic scheduler equipped with a simple counter and a clock-gating logic is used. A feedback control loop chooses the appropriate frequency and voltage pair based on the status of switch’s input FIFOs. We report results of simulation and synthesis on a 45nm CMOS technology.

A Simple DVFS Controller for a NoC Switch / Yadav, MANOJ KUMAR; Casu, MARIO ROBERTO; Zamboni, Maurizio. - ELETTRONICO. - (2012), pp. 131-134. ((Intervento presentato al convegno PRIME 2012 tenutosi a Aachen (D) nel 12-15 June 2012.

A Simple DVFS Controller for a NoC Switch

YADAV, MANOJ KUMAR;CASU, MARIO ROBERTO;ZAMBONI, Maurizio
2012

Abstract

Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but yet a costly one as far as power consumption is concerned. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. In its typical, bulky incarnation with voltage regulators and PLLs or DLLs for frequency synthesis, though, it does not fit very well the need for individual regulation at the level of NoC’s single switch. We propose a simple DVFS mechanism for a NoC switch. It uses just two voltages, high and low, for voltage scaling. For effective frequency scaling a periodic scheduler equipped with a simple counter and a clock-gating logic is used. A feedback control loop chooses the appropriate frequency and voltage pair based on the status of switch’s input FIFOs. We report results of simulation and synthesis on a 45nm CMOS technology.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2497548
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