Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral descriptions can be turned into real implementations, in terms of logic gates. Scheduling is one of the most time-consuming steps in the overall design flow, and may become much more complex when performing hardware synthesis from high-level specifications. Exploiting a single scheduling strategy on very large designs is often reductive and potentially inadequate. Furthermore, finding the “best” single candidate among all possible scheduling algorithms is practically infeasible. In this paper we introduce a hybrid scheduling approach, that is a preliminary step towards a comprehensive solution, not yet provided by industrial or by academic solutions. Our method relies on an abstract symbolic representation of data flow nodes (operations) bound to control flow paths: it produces a more realistic lower bound during the pre-scheduling resource estimation step and speeds up slower but accurate heuristic scheduling techniques, thus achieving a globally improved result.
|Titolo:||Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques|
|Data di pubblicazione:||2010|
|Digital Object Identifier (DOI):||10.1145/1698759.1698762|
|Appare nelle tipologie:||1.1 Articolo in rivista|