Archivio Istituzionale della RicercaThis paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.
Glitch power minimization by gate freezing / Benini, L; DE MICHELI, G; Macii, Alberto; Macii, Enrico; Poncino, Massimo; Scarsi, Riccardo. - (1999), pp. 163-167. (Intervento presentato al convegno DATE 99, Design, Automation and Test in Europe Conference and Exhibition 1999 tenutosi a Munich, Germany nel 9-12 March 1999) [10.1109/DATE.1999.761113].
Glitch power minimization by gate freezing
MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO;SCARSI, Riccardo
1999
Abstract
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/1870703
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo