The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype.

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology / Tota, Sergio Vincenzo; Casu, MARIO ROBERTO; Motto, P; RUO ROCH, Massimo; Zamboni, Maurizio. - ELETTRONICO. - (2007), pp. 1-4. ((Intervento presentato al convegno 2007 International Symposium on System-on-Chip tenutosi a Tampere, Finland nel 20-21 November, 2007 [10.1109/ISSOC.2007.4427429].

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology

TOTA, Sergio Vincenzo;CASU, MARIO ROBERTO;RUO ROCH, Massimo;ZAMBONI, Maurizio
2007

Abstract

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1672069
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