In this paper, we discuss the design and testing results of an analog 0.35 μm CMOS Turbo decoder for the rate-1/3, 40 bit, UMTS Turbo Code. The prototype was successfully tested at nominal conditions (2 Mbps), with an overall power consumption of 10.3 mW at 3.3 V. The tested BER curve shows a limited performance loss (about 0.5 dB) with respect to that of the digital implementation. We also discuss a discrete-time model of the analog decoder which allows to run BER simulations including circuit transient behavior and device mismatch in a very short time. Circuit-level simulations demonstrate the validity of our model. According to the discrete-time simulation, a significant contribution to the performance loss is due to device mismatch.

An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code / GRAELL I., AMAT A; Benedetto, Sergio; Montorsi, Guido; Vogrig, D; Neviani, A; Gerosa, A.. - 1:(2005), pp. 663-667. ((Intervento presentato al convegno IEEE International Conference on Communications [10.1109/ICC.2005.1494434].

An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code

BENEDETTO, Sergio;MONTORSI, Guido;
2005

Abstract

In this paper, we discuss the design and testing results of an analog 0.35 μm CMOS Turbo decoder for the rate-1/3, 40 bit, UMTS Turbo Code. The prototype was successfully tested at nominal conditions (2 Mbps), with an overall power consumption of 10.3 mW at 3.3 V. The tested BER curve shows a limited performance loss (about 0.5 dB) with respect to that of the digital implementation. We also discuss a discrete-time model of the analog decoder which allows to run BER simulations including circuit transient behavior and device mismatch in a very short time. Circuit-level simulations demonstrate the validity of our model. According to the discrete-time simulation, a significant contribution to the performance loss is due to device mismatch.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1533480
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