In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and efficient architecture for on-the-fly data compression and decompression whose field of operation is the cache-to-memory path. Uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills take place. We explore two classes of compression methods, profile-driven and differential, since they are characterized by compact HW implementations, and we compare their performance to those provided by some state-of-the-art compression methods (e.g., we have considered a few variants of the Lempel-Ziv encoder). We present experimental results about memory traffic and energy consumption in the cache-to-memory path of a core-based system running standard benchmark programs. The achieved average energy savings range from 4.2% to 35.2%, depending on the selected compression algorithm

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors / Benini, L; Bruni, D; Macii, Alberto; Macii, E.. - (2002), pp. 449-453. ((Intervento presentato al convegno DATE-02: IEEE Design Automation and Test in Europe tenutosi a Paris, France nel Marzo 2002 [10.1109/DATE.2002.998312].

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors

MACII, Alberto;MACII E.
2002

Abstract

In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and efficient architecture for on-the-fly data compression and decompression whose field of operation is the cache-to-memory path. Uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills take place. We explore two classes of compression methods, profile-driven and differential, since they are characterized by compact HW implementations, and we compare their performance to those provided by some state-of-the-art compression methods (e.g., we have considered a few variants of the Lempel-Ziv encoder). We present experimental results about memory traffic and energy consumption in the cache-to-memory path of a core-based system running standard benchmark programs. The achieved average energy savings range from 4.2% to 35.2%, depending on the selected compression algorithm
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500501
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