We propose an integrated front-end/back-end flow for the automatic generation of a multi-bank memory architecture for embedded systems. The flow is based on an algorithm for the automatic partitioning of on-chip SRAM. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back-annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%.

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip / Benini, L.; Macchiarulo, L.; Macii, Alberto; Macii, E.; Poncino, Massimo. - (2001), pp. 784-789. ((Intervento presentato al convegno DAC-38: ACM/IEEE Design Automation Conference tenutosi a Las Vegas, Nevada nel Giugno 2001 [10.1109/DAC.2001.156243].

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip

MACII, Alberto;E. MACII;PONCINO, MASSIMO
2001

Abstract

We propose an integrated front-end/back-end flow for the automatic generation of a multi-bank memory architecture for embedded systems. The flow is based on an algorithm for the automatic partitioning of on-chip SRAM. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back-annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500481
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