Memory-processor integration offers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. This option is especially effective when memory access patterns can be profiled and studied at design time (as in typical real-time embedded systems). In this work, we propose an algorithm for the automatic partitioning of on-chip SRAM in multiple banks that can be independently accessed. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm provides a globally optimum solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 42%.

A Recursive Algorithm for Low-Power Memory Partitioning / L., Benini; Macii, Alberto; Poncino, Massimo. - (2000), pp. 78-83. (Intervento presentato al convegno ISLPED-00: ACM/IEEE International Symposium on Low Power Electronics and Design tenutosi a Rapallo/Portofino Coast nel Luglio 2000) [10.1109/LPE.2000.155257].

A Recursive Algorithm for Low-Power Memory Partitioning

MACII, Alberto;PONCINO, MASSIMO
2000

Abstract

Memory-processor integration offers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. This option is especially effective when memory access patterns can be profiled and studied at design time (as in typical real-time embedded systems). In this work, we propose an algorithm for the automatic partitioning of on-chip SRAM in multiple banks that can be independently accessed. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm provides a globally optimum solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 42%.
2000
1581131909
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500477
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