System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional blocks. We focus on power estimation for data-dominated systems specified as synchronous data-flows and implemented on a single-processor architecture. Our estimator is integrated within the Ptolemy design environment, and provides information to system designers on the power dissipated by every task in a given specification. Power estimation is based on instruction-level power models. We demonstrate the applicability of our tool on a few design examples and target architectures.

Supporting system-level power exploration for DSP applications / L., Benini; M., Ferrero; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2000), pp. 17-22. ((Intervento presentato al convegno 10th Great Lakes Symposium on VLSI tenutosi a Evanston ILL (USA) nel March 2-4, 2000 [10.1145/330855.330945].

Supporting system-level power exploration for DSP applications

MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO
2000

Abstract

System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional blocks. We focus on power estimation for data-dominated systems specified as synchronous data-flows and implemented on a single-processor architecture. Our estimator is integrated within the Ptolemy design environment, and provides information to system designers on the power dissipated by every task in a given specification. Power estimation is based on instruction-level power models. We demonstrate the applicability of our tool on a few design examples and target architectures.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500472
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