Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a synthesis-based design flow poses the challenge of interfacing logic blocks in shutdown mode with active units: The outputs of inactive gates can float at intermediate voltages, causing very large short-circuit currents in the active gates they drive. In this paper, we propose two novel low-overhead elementary cells that fully address this issue. These cells can be added to any synthesis library, and they can be inserted into a netlist at the boundary between shutdown and active regions. Our results show that: (i) Our cells solve the interfacing problem with minimum overhead; (ii) A nonintrusive design flow enhancement is sufficient to automatically insert interface cells in post-synthesis netlists.

Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion / Babighian, P; Benini, L; Macii, Alberto; Macii, Enrico. - 1:(2006), pp. 126-131. ((Intervento presentato al convegno DATE '06: Design, Automation and Test in Europe, 2006. tenutosi a Monaco di Baviera nel Marzo 2006 [10.1109/DATE.2006.243770].

Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion

MACII, Alberto;MACII, Enrico
2006

Abstract

Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a synthesis-based design flow poses the challenge of interfacing logic blocks in shutdown mode with active units: The outputs of inactive gates can float at intermediate voltages, causing very large short-circuit currents in the active gates they drive. In this paper, we propose two novel low-overhead elementary cells that fully address this issue. These cells can be added to any synthesis library, and they can be inserted into a netlist at the boundary between shutdown and active regions. Our results show that: (i) Our cells solve the interfacing problem with minimum overhead; (ii) A nonintrusive design flow enhancement is sufficient to automatically insert interface cells in post-synthesis netlists.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/1500323
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