Implementation rules for iterative decoders of concatenated codes with interleavers are proposed based on a study of the quantization effects on the performance. We consider both cases of a single soft-input soft-output (SISO) module performing sequentially all iterations and of a pipelined structure in which a dedicated hardware is in charge of each SISO operation. In the last case, we show that a suitable rescaling of the extrinsic informations yields almost ideal performance with the same number of bits (5) representing both LLRs and extrinsic information at any decoder stage.
Design of fixed-point iterative decoders for concatenated codes with interleavers / Montorsi, Guido; Benedetto, Sergio. - 2:(2000), pp. 801-806. (Intervento presentato al convegno IEEE Global Telecommunications Conference (GLOBECOM 00) tenutosi a San Francisco nel Dicembre 2000).
Design of fixed-point iterative decoders for concatenated codes with interleavers
MONTORSI, Guido;BENEDETTO, Sergio
2000
Abstract
Implementation rules for iterative decoders of concatenated codes with interleavers are proposed based on a study of the quantization effects on the performance. We consider both cases of a single soft-input soft-output (SISO) module performing sequentially all iterations and of a pipelined structure in which a dedicated hardware is in charge of each SISO operation. In the last case, we show that a suitable rescaling of the extrinsic informations yields almost ideal performance with the same number of bits (5) representing both LLRs and extrinsic information at any decoder stage.Pubblicazioni consigliate
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https://hdl.handle.net/11583/1419414
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