We propose a design approach for serial concatenation of an outer convolutional code and an inner trellis code with multilevel amplitude/phase modulations using a bit-by-bit iterative decoding scheme. An example is given for throughput of 2 bits/sec/Hz with 2×8PSK modulation to clarify the approach. In this example, an 8-state outer code with rate 4/5 and a 2-state inner trellis code with 5 inputs and 2×8PSK outputs per trellis branch were used. The performance of this code with input block of 16384 bits is within 1.1 dB from the Shannon limit for 8PSK at a bit error probability of 5×10 -8 for 2 bits/sec/Hz with 10 iterations.

Serial concatenated trellis coded modulation with iterative decoding / Benedetto, S.; Divsalar, D.; Montorsi, Guido; Pollara, F.. - (1997), pp. 8-8. (Intervento presentato al convegno IEEE International Symposium on Information Theory 1997 tenutosi a Ulm nel 29 Jun-4 Jul 1997) [10.1109/ISIT.1997.612923].

Serial concatenated trellis coded modulation with iterative decoding

MONTORSI, Guido;
1997

Abstract

We propose a design approach for serial concatenation of an outer convolutional code and an inner trellis code with multilevel amplitude/phase modulations using a bit-by-bit iterative decoding scheme. An example is given for throughput of 2 bits/sec/Hz with 2×8PSK modulation to clarify the approach. In this example, an 8-state outer code with rate 4/5 and a 2-state inner trellis code with 5 inputs and 2×8PSK outputs per trellis branch were used. The performance of this code with input block of 16384 bits is within 1.1 dB from the Shannon limit for 8PSK at a bit error probability of 5×10 -8 for 2 bits/sec/Hz with 10 iterations.
1997
0780339568
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1414304
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