The increasing level of integration in VLSI technology amplifies the effects of parasitics, especially related to the interconnections. The IC designers must comply with noise tolerance of the logic gates to achieve reliable performance in VLSI circuits. CAD tools are therefore required to reduce the influence of self-induced noise (due to simultaneous switching of large number of interconnected gates) through the optimization of circuit topologies and transistor sizes. A new tool, based both on simulations and experimental characterizations is presented together with preliminary results.
A CAD tool for noise tolerance analysis of CMOS digital circuits / M. GRAZIANO; G. MASERA; G. PICCININI; M. RUO ROCH; M. ZAMBONI. - In: ALTA FREQUENZA - RIVISTA DI ELETTRONICA. - ISSN 1120-1908. - 10:6(1998), pp. 53-56.
|Titolo:||A CAD tool for noise tolerance analysis of CMOS digital circuits|
|Data di pubblicazione:||1998|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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