Archivio Istituzionale della RicercaNew design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach
RT-level ITC'99 benchmarks and first ATPG results / Corno, Fulvio; SONZA REORDA, Matteo; Squillero, Giovanni. - In: IEEE DESIGN & TEST OF COMPUTERS. - ISSN 0740-7475. - 17:3(2000), pp. 44-53. [10.1109/54.867894]
RT-level ITC'99 benchmarks and first ATPG results
CORNO, Fulvio;SONZA REORDA, Matteo;SQUILLERO, Giovanni
2000
Abstract
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach
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https://hdl.handle.net/11583/1398724
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