| Nome |
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New techniques for functional testing of microprocessor based systems, file e384c42f-99f0-d4b2-e053-9f05fe0a1d67
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811
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Development Flow for On-Line Core Self-Test of Automotive Microcontrollers, file e384c42e-4c8f-d4b2-e053-9f05fe0a1d67
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110
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A Flexible Framework for the Automatic Generation of SBST Programs, file e384c42e-cd91-d4b2-e053-9f05fe0a1d67
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97
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Test Time Minimization in Reconfigurable Scan Networks, file e384c42f-32d5-d4b2-e053-9f05fe0a1d67
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90
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An Optimized Test During Burn-In for Automotive SoC, file e384c42f-df54-d4b2-e053-9f05fe0a1d67
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86
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In-field Functional Test of CAN Bus Controllers, file e384c431-fc15-d4b2-e053-9f05fe0a1d67
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72
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Test of Reconfigurable Modules in Scan Networks, file e384c430-335a-d4b2-e053-9f05fe0a1d67
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59
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Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs, file e384c432-744b-d4b2-e053-9f05fe0a1d67
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53
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A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks, file e384c430-ff36-d4b2-e053-9f05fe0a1d67
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51
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About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications, file e384c430-9427-d4b2-e053-9f05fe0a1d67
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48
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On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification, file e384c432-70e7-d4b2-e053-9f05fe0a1d67
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45
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Evaluating the Code Encryption Effects on Memory Fault Resilience, file e384c432-326f-d4b2-e053-9f05fe0a1d67
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37
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Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network, file e384c432-93aa-d4b2-e053-9f05fe0a1d67
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36
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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks, file e384c430-db0d-d4b2-e053-9f05fe0a1d67
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34
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Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor, file e384c433-c664-d4b2-e053-9f05fe0a1d67
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33
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Fault-Independent Test-Generation for Software-Based Self-Testing, file e384c430-ddaf-d4b2-e053-9f05fe0a1d67
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32
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A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks, file e384c431-0a89-d4b2-e053-9f05fe0a1d67
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29
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Exploiting Active Learning for Microcontroller Performance Prediction, file e384c433-a77c-d4b2-e053-9f05fe0a1d67
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27
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement, file e384c433-fc0e-d4b2-e053-9f05fe0a1d67
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26
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Fault-Independent Test-Generation for Software-Based Self-Testing, file e384c432-5c73-d4b2-e053-9f05fe0a1d67
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25
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Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks, file e384c434-2ba3-d4b2-e053-9f05fe0a1d67
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23
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Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques, file e384c433-a77b-d4b2-e053-9f05fe0a1d67
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21
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Test, Reliability and Functional Safety trends for Automotive System-on-Chip, file e384c434-7998-d4b2-e053-9f05fe0a1d67
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19
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Test, Reliability and Functional Safety Trends for Automotive System-on-Chip, file 8ca85a99-2ac5-4a5b-962f-9164fb4fea5c
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18
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An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests, file e384c431-1604-d4b2-e053-9f05fe0a1d67
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15
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A machine learning-based approach to optimize repair and increase yield of embedded flash memories in automotive systems-on-chip, file e384c432-5c6f-d4b2-e053-9f05fe0a1d67
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15
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An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests, file e384c431-1603-d4b2-e053-9f05fe0a1d67
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14
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Comparing different approaches to the test of Reconfigurable Scan Networks, file e384c433-2237-d4b2-e053-9f05fe0a1d67
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14
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A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, file e384c432-7eb4-d4b2-e053-9f05fe0a1d67
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13
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A Multi-Label Active Learning Framework for Microcontroller Performance Screening, file 2f434b01-35e0-4759-b6cc-5e889c713bd8
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12
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Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries, file e384c434-ce25-d4b2-e053-9f05fe0a1d67
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10
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Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms, file fe6717fd-2f1e-4b54-8abd-021eab21a7be
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9
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About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications, file e384c430-335b-d4b2-e053-9f05fe0a1d67
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8
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Semi-Supervised Deep Learning for Microcontroller Performance Screening, file 98c671f9-40b8-4f80-a5f8-9a4de26c9144
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7
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A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers, file 2be6f881-30fd-4064-8404-321887a4d5d4
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6
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Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries, file e384c434-ed15-d4b2-e053-9f05fe0a1d67
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6
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Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data, file 72057a64-5622-443c-afd2-03e97e465782
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5
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Recent Trends and Perspectives on Defect-Oriented Testing, file 9f026920-2439-410b-b613-af7250a5fb72
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5
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Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters, file c0db7b49-2a14-4fc8-b6ea-42efbdf574b1
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5
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Industrial best practice: cases of study by automotive chip- makers, file e384c434-2b3a-d4b2-e053-9f05fe0a1d67
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5
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Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data, file 69b2b92e-a5a1-4d11-ab4a-4f278bd8804a
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4
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A Suite of IEEE 1687 Benchmark Networks, file e384c42f-73a6-d4b2-e053-9f05fe0a1d67
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4
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Improved Test Solutions for COTS-Based Systems in Space Applications, file e384c431-4cf3-d4b2-e053-9f05fe0a1d67
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4
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In-field Functional Test of CAN Bus Controllers, file e384c432-0e89-d4b2-e053-9f05fe0a1d67
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4
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A comparative overview of ATPG flows targeting traditional and cell-aware fault models, file f0cc4d52-2b15-430f-979d-567836a03c6f
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4
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A comparative overview of ATPG flows targeting traditional and cell-aware fault models, file 20686db5-af41-4359-9c2c-cb6d086ec533
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3
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Feature Selection for Cost Reduction in MCU Performance Screening, file 3e7822e8-536a-4281-be9a-03d0a59f3be1
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3
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Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors, file 85465e44-e558-40b1-8d4d-d9614881b686
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3
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A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors, file b39ba89f-634a-49c8-a048-aea1b8e3c2dd
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3
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Observability solutions for in-field functional test of processor-based systems, file e384c42e-4b42-d4b2-e053-9f05fe0a1d67
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3
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Test Time Minimization in Reconfigurable Scan Networks, file e384c42f-7b53-d4b2-e053-9f05fe0a1d67
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3
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Automated Test Program Reordering for Efficient SBST, file e384c42f-c3be-d4b2-e053-9f05fe0a1d67
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3
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Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs, file e384c432-3672-d4b2-e053-9f05fe0a1d67
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3
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New Perspectives on Core In-field Path Delay Test, file 02d02db9-831d-49c3-a432-0fe9b07320c1
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2
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Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults, file 2a7b77fc-c27a-4ad1-8163-ca498176ed9c
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2
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Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT, file 3b821d3b-5e25-4929-b9c9-8d0378925b91
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2
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Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms, file 93d2cd20-7879-4ea3-bb61-68b5ada2992d
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2
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Enabling Inter-Product Transfer Learning on MCU Performance Screening, file 97592cf8-c40e-4a7c-887c-2a5764ce29a9
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2
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Transfer Learning in MCU Performance Screening, file bf798141-bd4c-4ae4-a186-419511808a47
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2
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Software-based self-test techniques of computational modules in dual issue embedded processors, file e384c42d-c926-d4b2-e053-9f05fe0a1d67
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2
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On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors, file e384c42e-2f1f-d4b2-e053-9f05fe0a1d67
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2
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A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks, file e384c430-dd66-d4b2-e053-9f05fe0a1d67
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2
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Fault-Independent Test-Generation for Software-Based Self-Testing, file e384c432-6acd-d4b2-e053-9f05fe0a1d67
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2
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Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network, file e384c432-ae30-d4b2-e053-9f05fe0a1d67
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2
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Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors, file e384c433-d339-d4b2-e053-9f05fe0a1d67
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2
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Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement, file e384c433-fc0f-d4b2-e053-9f05fe0a1d67
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2
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Using Formal Methods to Support the Development of STLs for GPUs, file ed609920-89f1-464d-a376-68282bc9b70a
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2
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Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing, file f75a5a69-41e0-49ac-b82f-7725f130586f
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2
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Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing, file 09828ac2-e11d-4407-9e75-ec3469de914a
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1
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Recent Trends and Perspectives on Defect-Oriented Testing, file 138d8101-4ed3-481a-8355-7c634e02664a
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1
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Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques, file 13f88721-e26e-4918-8449-673e9acf0ffc
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1
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On the integration and hardening of Software Test Libraries in Real-Time Operating Systems, file 1a5d3e46-ad94-4a77-b1bd-caa65906cf05
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1
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Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters, file 31b99bfe-9b32-41b4-ae1b-fd4ec0fef6b8
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1
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Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT, file 51749749-b0ed-4a5c-ab8d-3e2ae52f456e
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1
|
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Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors, file 584f4738-9f47-4165-bfea-affdba8dcf12
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1
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A comparative overview of ATPG flows targeting traditional and cell-aware fault models, file 5fca03e1-ff4f-4614-8412-fc81342cd30e
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1
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Targeting different defect-oriented fault models in IC testing: an experimental approach, file 61b1b969-5b99-44ba-8cd6-79664cf81722
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1
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Enabling Inter-Product Transfer Learning on MCU Performance Screening, file 61c94669-ac89-48ee-9b54-d48356800826
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1
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Test, Reliability and Functional Safety Trends for Automotive System-on-Chip, file 86aa7109-84fe-4ecf-acc9-c9d1b8069e9d
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1
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Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques, file 87d25a00-bb79-44a9-9930-b554473aa4fb
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1
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Using Formal Methods to Support the Development of STLs for GPUs, file a91df840-21a3-4f3d-9dc6-edc9ae4c8843
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1
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Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs, file e384c42d-c651-d4b2-e053-9f05fe0a1d67
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1
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On the Maximization of the Sustained Switching Activity in a Processor, file e384c42d-ca98-d4b2-e053-9f05fe0a1d67
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1
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On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors, file e384c42e-28b2-d4b2-e053-9f05fe0a1d67
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1
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Observability solutions for in-field functional test of processor-based systems: a survey and quantitative test case evaluation, file e384c42f-08aa-d4b2-e053-9f05fe0a1d67
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1
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Software-Based Self-Test Techniques for Dual-Issue Embedded Processors, file e384c42f-bcec-d4b2-e053-9f05fe0a1d67
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1
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On the Automatic Generation of SBST Test Programs for In-Field Test, file e384c42f-c1ff-d4b2-e053-9f05fe0a1d67
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1
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On the Functional Test of the Cache Coherency Logic in Multi-core Systems, file e384c42f-c20c-d4b2-e053-9f05fe0a1d67
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1
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On the Optimization of SBST Test Program Compaction, file e384c42f-c2c7-d4b2-e053-9f05fe0a1d67
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1
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An evolutionary technique for reducing the duration of reconfigurable scan network test, file e384c430-3359-d4b2-e053-9f05fe0a1d67
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1
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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks, file e384c431-05f8-d4b2-e053-9f05fe0a1d67
|
1
|
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On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification, file e384c431-8cc6-d4b2-e053-9f05fe0a1d67
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1
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Evaluating the Code Encryption Effects on Memory Fault Resilience, file e384c432-45ac-d4b2-e053-9f05fe0a1d67
|
1
|
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A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, file e384c432-7eb5-d4b2-e053-9f05fe0a1d67
|
1
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A machine learning-based approach to optimize repair and increase yield of embedded flash memories in automotive systems-on-chip, file e384c432-81b9-d4b2-e053-9f05fe0a1d67
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1
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An Optimized Test During Burn-In for Automotive SoC, file e384c432-edc1-d4b2-e053-9f05fe0a1d67
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1
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A Flexible Framework for the Automatic Generation of SBST Programs, file e384c432-f398-d4b2-e053-9f05fe0a1d67
|
1
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Development Flow for On-Line Core Self-Test of Automotive Microcontrollers, file e384c433-3167-d4b2-e053-9f05fe0a1d67
|
1
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Exploiting Active Learning for Microcontroller Performance Prediction, file e384c433-a81b-d4b2-e053-9f05fe0a1d67
|
1
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New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core, file e384c433-de9b-d4b2-e053-9f05fe0a1d67
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1
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| Totale |
2.137 |
Archivio Istituzionale della Ricerca