| Nome |
# |
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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals, file e384c42d-f0f6-d4b2-e053-9f05fe0a1d67
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1682
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Energy Optimization at the MAC Layer for a Forest Fire Monitoring Wireless Sensor Network, file e384c430-531e-d4b2-e053-9f05fe0a1d67
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1339
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FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels, file e384c42e-22ad-d4b2-e053-9f05fe0a1d67
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899
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A routing-algorithm-aware design tool for indoor wireless sensor networks, file e384c42e-1ffb-d4b2-e053-9f05fe0a1d67
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817
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Desynchronization: Synthesis of asynchronous circuits from synchronous specifications, file e384c42d-f553-d4b2-e053-9f05fe0a1d67
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815
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Leveraging BIM Interoperability for UWB-Based WSN Planning, file e384c42d-c7ec-d4b2-e053-9f05fe0a1d67
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624
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An Energy and Memory-Efficient Key Management Scheme for Mobile Heterogeneous Sensor Networks, file e384c42e-12cb-d4b2-e053-9f05fe0a1d67
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622
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An Efficient Data Aggregation Algorithm for Cluster-based Sensor Network, file e384c42e-0353-d4b2-e053-9f05fe0a1d67
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567
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Energy-aware parallelization flow and toolset for C code, file e384c42e-322b-d4b2-e053-9f05fe0a1d67
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541
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Realistic performance-constrained pipelining in high-level synthesis, file e384c42e-2267-d4b2-e053-9f05fe0a1d67
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507
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Designing parameterizable hardware IPs in a model-based design environment for high-level synthesis, file e384c42f-0ab6-d4b2-e053-9f05fe0a1d67
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497
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Interactive Trace-Based Analysis Toolset for Manual Parallelization of C Programs, file e384c42e-395e-d4b2-e053-9f05fe0a1d67
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468
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Dynamic Trace-Based Data Dependency Analysis for Parallelization of C Programs, file e384c42e-22ac-d4b2-e053-9f05fe0a1d67
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453
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A comparison of software platforms for Wireless Sensor Networks: MANTIS, TinyOS and ZigBee, file e384c42e-08b6-d4b2-e053-9f05fe0a1d67
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424
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SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits, file e384c42d-c627-d4b2-e053-9f05fe0a1d67
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369
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Routing-aware design of indoor wireless sensor networks using an interactive tool, file e384c42f-0ab4-d4b2-e053-9f05fe0a1d67
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361
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Exploiting area/delay tradeoffs in high-level synthesis, file e384c42e-2266-d4b2-e053-9f05fe0a1d67
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360
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A Secure Online Key Establishment Scheme for Mobile Heterogeneous Sensor Networks, file e384c42e-3be0-d4b2-e053-9f05fe0a1d67
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359
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Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis, file e384c430-0194-d4b2-e053-9f05fe0a1d67
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336
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Online Authentication and Key Establishment Scheme for Heterogeneous Sensor Networks, file e384c42e-3bdf-d4b2-e053-9f05fe0a1d67
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335
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Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis, file e384c42f-b64c-d4b2-e053-9f05fe0a1d67
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285
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ECOSCALE: Reconfigurable computing and runtime system for future exascale systems, file e384c42f-75fe-d4b2-e053-9f05fe0a1d67
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274
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High-level Synthesis for Semi-global Matching: Is the juice worth the squeeze?, file e384c42f-7407-d4b2-e053-9f05fe0a1d67
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260
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Capacitive sensor for tagless remote human identification using body frequency absorption signatures, file e384c430-38a9-d4b2-e053-9f05fe0a1d67
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255
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Long range, high sensitivity, low noise capacitive sensor for tagless indoor human localization, file e384c430-47f7-d4b2-e053-9f05fe0a1d67
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244
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Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project, file e384c430-5712-d4b2-e053-9f05fe0a1d67
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241
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A Contactless Sensor for Human Body Identification using RF Absorption Signatures, file e384c42f-fcd3-d4b2-e053-9f05fe0a1d67
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240
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A Symbolic Approach for the Combined Solution of Scheduling and Allocation, file e384c430-5768-d4b2-e053-9f05fe0a1d67
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225
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Software performance estimation strategies in a system-level design tool, file e384c430-3abd-d4b2-e053-9f05fe0a1d67
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224
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An Authentication and Key Establishment Scheme for the IP-Based Wireless Sensor Networks, file e384c42e-1ae7-d4b2-e053-9f05fe0a1d67
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223
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LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow, file e384c430-26dd-d4b2-e053-9f05fe0a1d67
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220
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High sensitivity, low noise front-end for long range capacitive sensors for tagless indoor human localization, file e384c430-398a-d4b2-e053-9f05fe0a1d67
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199
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Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL, file e384c430-06e3-d4b2-e053-9f05fe0a1d67
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198
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Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications, file e384c430-3bb2-d4b2-e053-9f05fe0a1d67
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177
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HEAP: A Highly Efficient Adaptive multi-Processor framework, file e384c42e-2943-d4b2-e053-9f05fe0a1d67
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173
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Compilation-based software performance estimation for system level design, file e384c430-398c-d4b2-e053-9f05fe0a1d67
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167
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HEAP: A Highly Efficient Adaptive Multi-processor Framework, file e384c42e-22ae-d4b2-e053-9f05fe0a1d67
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165
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High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis, file e384c430-0b11-d4b2-e053-9f05fe0a1d67
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161
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Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL, file e384c430-0b29-d4b2-e053-9f05fe0a1d67
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121
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Performance and energy-efficient implementation of a smart city application on FPGAs, file e384c430-3bb7-d4b2-e053-9f05fe0a1d67
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63
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A Tagless Indoor Localization System Based on Capacitive Sensing Technology, file e384c432-2de8-d4b2-e053-9f05fe0a1d67
|
61
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Wireless Sensor Networks, file e384c42f-a7ad-d4b2-e053-9f05fe0a1d67
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60
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Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project, file e384c432-57ab-d4b2-e053-9f05fe0a1d67
|
47
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Neural Networks for Indoor Person Tracking With Infrared Sensors, file e384c432-d649-d4b2-e053-9f05fe0a1d67
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46
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Performance of machine learning classifiers for indoor person localization with capacitive sensors, file e384c433-85be-d4b2-e053-9f05fe0a1d67
|
46
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Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms, file e384c430-dcaa-d4b2-e053-9f05fe0a1d67
|
44
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CNN-on-AWS: Efficient Allocation of Multi-Kernel Applications on Multi-FPGA Platforms, file e384c431-eaa9-d4b2-e053-9f05fe0a1d67
|
39
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High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs, file e384c433-6796-d4b2-e053-9f05fe0a1d67
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37
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An optimizing C front-end for hardware synthesis, file e384c430-426d-d4b2-e053-9f05fe0a1d67
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34
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Neural network-based indoor tag-less localization using capacitive sensors, file e384c431-501e-d4b2-e053-9f05fe0a1d67
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31
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EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications, file e384c42e-3005-d4b2-e053-9f05fe0a1d67
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30
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|
Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis, file e384c432-37e0-d4b2-e053-9f05fe0a1d67
|
28
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Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms, file e384c432-6184-d4b2-e053-9f05fe0a1d67
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28
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Neural Networks for Indoor Human Activity Reconstructions, file e384c432-640e-d4b2-e053-9f05fe0a1d67
|
25
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Verification of Similar FSMs by Mixing Incremental Re-encoding Reachability Analysis and Combinational Checks, file e384c42d-e032-d4b2-e053-9f05fe0a1d67
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22
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Fast Energy-Optimal Multi-Kernel DNN-like Application Allocation on Multi-FPGA Platforms, file e384c434-2db5-d4b2-e053-9f05fe0a1d67
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21
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Capacitive sensor and method for sensing changes in a space, file e384c434-5ff0-d4b2-e053-9f05fe0a1d67
|
21
|
|
High-level Synthesis for Semi-global Matching: Is the juice worth the squeeze?, file e384c432-6e66-d4b2-e053-9f05fe0a1d67
|
19
|
|
FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio, file 54d99630-b4f9-4626-8da5-bcfd0bd1b0b6
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12
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Neural network-based indoor tag-less localization using capacitive sensors, file e384c430-f89c-d4b2-e053-9f05fe0a1d67
|
10
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Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs, file 1b6ec5f4-084d-40aa-880b-afab53091bb7
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7
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Drift Rejection Differential Frontend for Single Plate Capacitive Sensors, file 8e29245e-0f1b-40a9-8f44-f5afd5ea2ce7
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6
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Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops, file 7763dd14-24f6-47b7-9778-4937ca7b7351
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5
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Neural Networks for Indoor Human Activity Reconstructions, file e384c432-34e1-d4b2-e053-9f05fe0a1d67
|
5
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|
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs, file c79f8d39-ff36-4201-8180-9a87740080fd
|
4
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|
Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications, file e384c430-42be-d4b2-e053-9f05fe0a1d67
|
4
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|
FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio, file 380f950c-ad32-48c6-a980-372d4abf4385
|
3
|
|
Long range, high sensitivity, low noise capacitive sensor for tagless indoor human localization, file e384c432-45e6-d4b2-e053-9f05fe0a1d67
|
3
|
|
A Model-Based Approach for Bridging Virtual and Physical Sensor Nodes in a Hybrid Simulation Framework, file e384c42e-3235-d4b2-e053-9f05fe0a1d67
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2
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|
Energy Optimization at the MAC Layer for a Forest Fire Monitoring Wireless Sensor Network, file e384c432-329e-d4b2-e053-9f05fe0a1d67
|
2
|
|
Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project, file e384c432-329f-d4b2-e053-9f05fe0a1d67
|
2
|
|
Wireless Sensor Networks, file e384c432-45ec-d4b2-e053-9f05fe0a1d67
|
2
|
|
A Contactless Sensor for Human Body Identification using RF Absorption Signatures, file e384c432-5ee5-d4b2-e053-9f05fe0a1d67
|
2
|
|
Energy-aware parallelization flow and toolset for C code, file e384c432-7228-d4b2-e053-9f05fe0a1d67
|
2
|
|
HEAP: A Highly Efficient Adaptive multi-Processor framework, file e384c432-7229-d4b2-e053-9f05fe0a1d67
|
2
|
|
High sensitivity, low noise front-end for long range capacitive sensors for tagless indoor human localization, file e384c432-722e-d4b2-e053-9f05fe0a1d67
|
2
|
|
Interactive Trace-Based Analysis Toolset for Manual Parallelization of C Programs, file e384c432-7c35-d4b2-e053-9f05fe0a1d67
|
2
|
|
CNN-on-AWS: Efficient Allocation of Multi-Kernel Applications on Multi-FPGA Platforms, file e384c432-9909-d4b2-e053-9f05fe0a1d67
|
2
|
|
Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms, file e384c432-b124-d4b2-e053-9f05fe0a1d67
|
2
|
|
Neural Networks for Indoor Person Tracking With Infrared Sensors, file e384c432-c335-d4b2-e053-9f05fe0a1d67
|
2
|
|
Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework, file e384c42e-2f2e-d4b2-e053-9f05fe0a1d67
|
1
|
|
High-Level Internet of Things Applications Development Using Wireless Sensor Networks, file e384c42e-3959-d4b2-e053-9f05fe0a1d67
|
1
|
|
Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms, file e384c430-ceff-d4b2-e053-9f05fe0a1d67
|
1
|
|
High-Level Internet of Things Applications Development Using Wireless Sensor Networks, file e384c432-426f-d4b2-e053-9f05fe0a1d67
|
1
|
|
Capacitive sensor for tagless remote human identification using body frequency absorption signatures, file e384c432-5d74-d4b2-e053-9f05fe0a1d67
|
1
|
|
HEAP: A Highly Efficient Adaptive Multi-processor Framework, file e384c432-5f38-d4b2-e053-9f05fe0a1d67
|
1
|
|
Fast Energy-Optimal Multi-Kernel DNN-like Application Allocation on Multi-FPGA Platforms, file e384c434-a671-d4b2-e053-9f05fe0a1d67
|
1
|
| Totale |
17219 |
Archivio Istituzionale della Ricerca