AMARETTO, Accelerating Quantum Algorithm Development With FPGA Emulation

In recent decades, Quantum Computing (QC) has gained widespread attention among researchers and industries, driven by its potential to outperform classical systems in several key areas. However, validating novel quantum algorithms poses substantial challenges due to limited qubit availability and noise in current quantum devices. Although software simulators are frequently employed to validate quantum circuits, they are timeconsuming and require high memory availability since as the number of qubits increases, the memory occupation grows exponentially. Hardware emulators have recently emerged as a faster, more efficient, cost-effective alternative. This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), a new architecture designed to improve quantum computing emulation on resource-constrained Field-Programmable Gate Arrays (FPGAs). To provide a flexible and complete tool for quantum algorithm development, the emulator supports two universal gate sets, Clifford+T and rotational. AMARETTO mimics quantum computing's inherent parallelism through multiple concurrent processing elements, achieving high throughput by harnessing the sparse nature of the gate matrices, coupled with pipelining in a Reduced Instruction Set Computer (RISC)-like architecture. A dedicated compiler translates OpenQASM 2.0 into AMARETTO's instructions, enabling support for custom gates leveraging the equivalences known in the literature. Experimental results on an AMD Zynq UltraScale+ MPSoC ZCU106 demonstrate successful emulation of quantum circuits up to eighteen qubits with a throughput of 12.207kgates s , validated against Qiskit simulators. Our evaluation confirms competitive performance with existing FPGA-based emulators in terms of throughput and scalability, while targeting an affordable FPGA platform.