Predictable and Scalable Analog Matrix–Vector Multiplication in Memristor Crossbars via Closed-Form Wire-Resistance Compensation

Wire resistance in memristor crossbars introduces geometry-dependent voltage attenuation that degrades analog matrix–vector multiplication (MVM), while parasitic sneak paths further distort output currents as array dimensions scale. Here, we develop a closed-form distributed line-resistance model that jointly accounts for horizontal and vertical interconnects as well as parasitic conduction, yielding explicit node-voltage profiles and a compact analytical description of how interconnect losses modify the effective conductance matrix. Leveraging this predictive framework, computation is kept fully analog and two low-overhead correction strategies are introduced: (i) a geometry-aware adjustment of the programmed conductances derived directly from the analytically computed wire-resistance error; and (ii) a four-configuration symmetry-averaging scheme that suppresses residual spatial non-uniformities without requiring any modification to peripheral circuits. Circuit-and task-level evaluations on crossbar arrays demonstrate that, once compensated, MVM errors remain bounded and no longer scale with array size, while accuracy is preserved with a constant corrective overhead of four MVMs per elementary array block, validated up to 128 × 128 arrays. By fixing the problem class, correction targets are computed analytically and reused, replacing iterative tuning with predictable operation, and enabling reliable analog in-memory computing at scale.