Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS

The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 μ m2 and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just 3.3 μ W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOMA) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800μ m2 and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB).