Structured Model Order Reduction of System-Level Power Delivery Networks

This paper proposes a comprehensive model order reduction framework to enable fast power integrity verification at the system level. This approach is developed to compress models of complete power delivery networks of high-end multiprocessor systems, where electromagnetic models of board and package are connected through banks of per-core Fully Integrated Voltage Regulators to chip models and loads in a closed-loop configuration. Due to complexity in both dynamical behavior and number of signals to be monitored, a direct transient simulation at the system level is very challenging. We show that a careful topological formulation of the circuit equations leads to a global model format that enables a structured projection framework for the elimination of the redundant states. Within this framework, we present and compare two alternative approaches based on approximate interpolation and empirical balancing, here adapted for the application at hand. In both cases, the resulting system is proven to be unconditionally stable both in open and in closed-loop configuration. Transient simulation of the reduced system provides a speedup exceeding 100× with respect to SPICE.