This work presents the development of a 64-channel application-specific integrated circuit (ASIC), implemented to detect the optical Cherenkov light from sub-orbital and orbital altitudes. These kinds of signals are generated by ultra-high energy cosmic rays (UHECRs) and cosmic neutrinos (CNs). The purpose of this front-end electronics is to provide a readout unit for a matrix of silicon photo-multipliers (SiPMs) to identify extensive air showers (EASs). Each event can be stored into a configurable array of 256 cells where the on-board digitization can take place with a programmable 12-bits Wilkinson analog-to-digital converter (ADC). The sampling, the conversion process, and the main digital logic of the ASIC run at 200 MHz, while the readout is managed by dedicated serializers operating at 400 MHz in double data rate (DDR). The chip is designed in a commercial 65 nm CMOS technology, ensuring a high configurability by selecting the partition of the channels, the resolution in the interval 8–12 bits, and the source of its trigger. The production and testing of the ASIC is planned for the forthcoming months.

A Configurable 64-Channel ASIC for Cherenkov Radiation Detection from Space / Di Salvo, Andrea; Garbolino, Sara; Mignone, Marco; Zugravel, Stefan Cristi; Rivetti, Angelo; Bertaina, Mario Edoardo; Palmieri, Pietro Antonio. - In: INSTRUMENTS. - ISSN 2410-390X. - ELETTRONICO. - 7:4(2023). [10.3390/instruments7040050]

A Configurable 64-Channel ASIC for Cherenkov Radiation Detection from Space

Di Salvo, Andrea;Zugravel, Stefan Cristi;
2023

Abstract

This work presents the development of a 64-channel application-specific integrated circuit (ASIC), implemented to detect the optical Cherenkov light from sub-orbital and orbital altitudes. These kinds of signals are generated by ultra-high energy cosmic rays (UHECRs) and cosmic neutrinos (CNs). The purpose of this front-end electronics is to provide a readout unit for a matrix of silicon photo-multipliers (SiPMs) to identify extensive air showers (EASs). Each event can be stored into a configurable array of 256 cells where the on-board digitization can take place with a programmable 12-bits Wilkinson analog-to-digital converter (ADC). The sampling, the conversion process, and the main digital logic of the ASIC run at 200 MHz, while the readout is managed by dedicated serializers operating at 400 MHz in double data rate (DDR). The chip is designed in a commercial 65 nm CMOS technology, ensuring a high configurability by selecting the partition of the channels, the resolution in the interval 8–12 bits, and the source of its trigger. The production and testing of the ASIC is planned for the forthcoming months.
2023
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2984434