As System-on-Chips become more and more com- plex, a high fault coverage is becoming more difficult to achieve. As fault coverage is the de facto standard metric for testing, we aim for a faster heuristic for test evaluations. In particular, last year a faster heuristic known as connectivity was defined in ITC 2022 [1]. We want to improve over this heuristic, trying to improve the precision of the connectivity metric. In particular, we introduce a bit-level connectivity, using the general connectivity as an optimistic value, however taking into account the toggle coverage at a register-level. Our case study is a chip developed by STMicroelectronics of the SP58 family.

Taking Test Programs Connectivity to the Bit-Level / Calabrese, Andrea. - (In corso di stampa). (Intervento presentato al convegno IEEE European Test Symposium, (ETS)).

Taking Test Programs Connectivity to the Bit-Level

Andrea Calabrese
In corso di stampa

Abstract

As System-on-Chips become more and more com- plex, a high fault coverage is becoming more difficult to achieve. As fault coverage is the de facto standard metric for testing, we aim for a faster heuristic for test evaluations. In particular, last year a faster heuristic known as connectivity was defined in ITC 2022 [1]. We want to improve over this heuristic, trying to improve the precision of the connectivity metric. In particular, we introduce a bit-level connectivity, using the general connectivity as an optimistic value, however taking into account the toggle coverage at a register-level. Our case study is a chip developed by STMicroelectronics of the SP58 family.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2981871