pMOS-only pW-power voltage reference with sub-10 ppm/°C trimmed temperature coefficient and sub-100 ppm/V line sensitivity

In this paper, a new ultra-low-power voltage reference based on a two-stage,all-pMOS topology operating in the subthreshold region is proposed touniquely meet the pW-power range power consumption requirements ofemerging Internet-of-Things applications without significantly compromisingthe temperature coefficient (TC) and the line sensitivity (LS) performance. The proposed circuit consists of the LS regulator, TC corrector, and TC trimmingsections. Based on post-layout Monte Carlo simulations in 180-nm CMOS, theproposed circuit operates with 0.8- to 2.4-V supply potential and generates areference voltage of 206 mV with a process spread of 7.8%, achieving an aver-age calibrated TC of 4.4 ppm/°C in the temperature range of -20°C to 80°C, and an average LS of 51.5 ppm/V with a power consumption of 25.9 pW at 25°C (469.1 pW at 80°C).