Titanium-based buffer layers for BEoL-compatible resistive memories

Resistive switching (RS) devices are considered key players for next generation memories. Especially, their compatibility with back-end of line (BEoL) processes makes such devices good candidates for integration in complementary Metal-Oxide-Semiconductor (CMOS) technology. However, systematic investigations providing new design rules are still needed before achieving large-scale embedded application. This project deals with RS memories employing different Ti-based buffer layers and a typical BEoL-compatible metal like tungsten. In order to investigate the impact titanium has on the electrical performances, both DC and pulsed operation regimes are tested. A statistical analysis is carried out on a set of devices for each buffer layer (referred to as NoBuffer, mixBuffer, Buffer1, Buffer3 and Buffer5).