Racetrack memories are promising candidates for next-generation solid-state storage devices. Various racetrack memories have been proposed in the literature, skyrmion based or domain wall based. However, none of them show integrated computing capabilities. Here, we introduce a new domain wall based racetrack concept that can operate both as a memory and as a computing device. The computation is defined by changing locally the anisotropy of the film. Stray fields from nearby cells are exploited to implement reconfigurable logic gates. We demonstrate that the racetrack array can operate in parallel in every cell. This is achieved by an external out-of-plane Zeeman field applied to the array. As proof-of-principle, we verified the single computing cell and multiple connected cells operating in parallel by micromagnetic simulations. Logic NAND/NOR is implemented independently in every computing cell. This study provides the guidelines for the development and optimization of this family of logic gates.

Parallel Computation in the Racetrack Memory / Riente, Fabrizio; Turvani, Giovanna; Vacca, Marco; Graziano, Mariagrazia. - In: IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING. - ISSN 2168-6750. - ELETTRONICO. - 10:2(2022), pp. 1216-1221. [10.1109/TETC.2021.3078061]

Parallel Computation in the Racetrack Memory

Riente, Fabrizio;Turvani, Giovanna;Vacca, Marco;Graziano, Mariagrazia
2022

Abstract

Racetrack memories are promising candidates for next-generation solid-state storage devices. Various racetrack memories have been proposed in the literature, skyrmion based or domain wall based. However, none of them show integrated computing capabilities. Here, we introduce a new domain wall based racetrack concept that can operate both as a memory and as a computing device. The computation is defined by changing locally the anisotropy of the film. Stray fields from nearby cells are exploited to implement reconfigurable logic gates. We demonstrate that the racetrack array can operate in parallel in every cell. This is achieved by an external out-of-plane Zeeman field applied to the array. As proof-of-principle, we verified the single computing cell and multiple connected cells operating in parallel by micromagnetic simulations. Logic NAND/NOR is implemented independently in every computing cell. This study provides the guidelines for the development and optimization of this family of logic gates.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2898872