Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations and susceptibility in different processor configurations with data accessing patterns are investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

Investigation of Single Event Effect in 28nm System-on-Chip with Multi Patterns / Yang, Weitao; Li, Yong-hong; Guo, Ya-xin; Zhao, Hao-yu; Li, Yang; Li, Pei; He, Chao-hui; Guo, Gang; Liu, Jie; Yang, Sheng-Sheng; An, Heng. - In: CHINESE PHYSICS B. - ISSN 1674-1056. - ELETTRONICO. - (2020). [10.1088/1674-1056/ab99b8]

Investigation of Single Event Effect in 28nm System-on-Chip with Multi Patterns

Yang, Weitao;
2020

Abstract

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations and susceptibility in different processor configurations with data accessing patterns are investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2846405