Optical ﬂow calculation algorithms are hard to implement on the hardware level in real-time, due to their complexity and high computational load. Therefore, presented works in the Literature focusing on the hardware implementation are limited. In this paper, we present a hierarchical block matching-based optical ﬂow algorithm suitable for real-time hardware implementation. The algorithm estimates the initial optical ﬂow with block matching and reﬁnes the vectors with local smoothness constraints in each level. We evaluate the proposed algorithm with novel data sets and provide results compared with the ground truth optical ﬂow. Furthermore, we present a reconﬁgurable hardware architecture of the proposed algorithm for calculating the optical ﬂow in real-time. The presented system can process 640×480 resolution frames at 39 frames/s.
|Titolo:||FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation|
|Data di pubblicazione:||2018|
|Digital Object Identifier (DOI):||10.1109/TCSVT.2016.2598703|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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