Conventional integrated circuits' design uses one layer to place logic gates and many additional layers to route interconnections. This design technique is built around the constraints of MOSFET transistors. To further improve the performance of integrated circuits, it is necessary to go beyond this limitation and to design true 3-D circuits. Although this possibility is difficult to implement with transistor technology, perpendicular nanomagnet logic (pNML) intrinsically enables the design of 3-D devices. It is very low-power consumption and offers the possibility to be integrated in the back end of traditional fabrication processes. These characteristics make pNML an ideal candidate to implement low-power coprocessors. In this paper, we demonstrate the possibilities offered by pNML technology by designing a 3-D coprocessor for the summed-area table, one of the most common algorithms used in image processing. We demonstrate the effectiveness of the design and the technology itself by comparing the performance with transistor implementations. The 3-D design makes it possible to obtain a small circuit footprint. Overall, the results presented here are a great step forward toward the design of 3-D coprocessors in pNML technology.
|Titolo:||Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology|
|Data di pubblicazione:||2019|
|Digital Object Identifier (DOI):||10.1109/TVLSI.2019.2905686|
|Appare nelle tipologie:||1.1 Articolo in rivista|