Algorithms used in microwave imaging for breast cancer detection require hardware acceleration to speedup execution time and reduce power consumption. In this paper we present the hardware implementation of two accelerators for two alternative imaging algorithms that we obtain entirely from SystemC specifications via high-level synthesis. The two algorithms present opposite characteristics that stress the design process and the capabilities of commercial HLS tools in different ways: the first is communication-bound and requires overlapping and pipelining of communication and computation in order to maximize the application throughput; the second is computation-bound and uses complex mathematical functions that HLS tools do not directly support. Despite these difficulties, thanks to HLS in the span of four months only we were able to explore a large design space and derive about one hundred implementations with different cost-performance profiles, targeting both an FPGA platform and a 32-nm standard-cell ASIC library. In addition, we could obtain results that outperform a previous RTL implementation, which confirms the remarkable progress of HLS tools.
|Titolo:||Accelerators for Breast Cancer Detection|
|Data di pubblicazione:||2017|
|Digital Object Identifier (DOI):||10.1145/2983630|
|Appare nelle tipologie:||1.1 Articolo in rivista|