NAND flash memories are used in large number of electronic devices for storing data. The ever increasing demand of the high storage in these devices has resulted in high density NAND flash memories. The high density is achieved through the process of continuous technology scaling and the use of multilevel cell (MLC) technology. In multilevel cell technology more than one bits are stored in a single cell of the flash memory. However, this increased storage density has come at a price of reduced reliability. The raw bit error rate has increased rapidly in high density flash memories, therefore, demanding more powerful error correcting codes. The bit error rate (BER) requirements in NAND flash memories are reported to be 10^−13 to 10^−16, after applying the error correcting code. The current practice is to use the hard decision error correcting codes in NAND flash memories, such as BCH codes. However, as the raw bit error rate is getting worse, these hard decision codes will not be able to achieve the BER requirements of these memories. Therefore, more powerful error correcting codes with soft decision decoding algorithm are required. Among the soft decision codes, low density parity check codes (LDPC) can be a promising candidate for error correction in high density NAND flash memories due to their excellent error correction performance close to the Shannon limit. LDPC codes employed in NAND flash memories have large block lengths and very high code rate and should show good error correcting and error floor performance. Evaluating the error floor performance of these codes at very low frame error rates, typically around 10^−9 to 10^−10, require the use of high speed hardware simulators. Due to the reconfigurability and high speed, field programmable gate arrays (FPGAs) are largely used for evaluating the performance of LDPC codes. This thesis presents an FPGA based simulator system for evaluating the error correction and error floor performance of regular quasi cyclic (QC) LDPC Codes, for the application of large page size MLC NAND flash memories. Particularly, we targeted the algebraic QC-LDPC codes, which have high code rates and good error correcting and error floor performance. A generalized, high throughput and resource efficient hardware implementation of the QC-LDPC encoder and the decoder is given on FPGA. The proposed decoder can decode any regular QC-LDPC code including very high circulant weight QC-LDPC codes, such as euclidean geometry (EG) LDPC codes. The generalized and high throughput implementation of such large circulant weight QC-LDPC codes is not reported previously in the open literature. Moreover, the encoder and decoder hardware implementations are given on FPGA for very large page size (8 KB) of NAND flash memory, which are also not dealt previously in the open literature. A high speed and high quality floating point additive white Gaussian noise channel is implemented on FPGA using the high level synthesis method. The high level synthesis is used to rapidly prototype the channel on FPGA and to lower the development time of the LDPC simulator system. The very low consumption of the logic resources by the channel also enabled us to instantiate many channel modules in parallel, resulting in high throughput of the simulator. This thesis also presents the FPGA implementation and simulation results of two algebraic QC-LDPC codes for the page size 8 KB of NAND flash memory. Simulation results show good error correcting and error floor performance of the developed codes making them a promising candidate for error correction in NAND flash memories.

Design of LDPC Decoder for Error Correction in Memory Devices / Zaidi, SYED AZHAR ALI. - (2015).

Design of LDPC Decoder for Error Correction in Memory Devices

ZAIDI, SYED AZHAR ALI
2015

Abstract

NAND flash memories are used in large number of electronic devices for storing data. The ever increasing demand of the high storage in these devices has resulted in high density NAND flash memories. The high density is achieved through the process of continuous technology scaling and the use of multilevel cell (MLC) technology. In multilevel cell technology more than one bits are stored in a single cell of the flash memory. However, this increased storage density has come at a price of reduced reliability. The raw bit error rate has increased rapidly in high density flash memories, therefore, demanding more powerful error correcting codes. The bit error rate (BER) requirements in NAND flash memories are reported to be 10^−13 to 10^−16, after applying the error correcting code. The current practice is to use the hard decision error correcting codes in NAND flash memories, such as BCH codes. However, as the raw bit error rate is getting worse, these hard decision codes will not be able to achieve the BER requirements of these memories. Therefore, more powerful error correcting codes with soft decision decoding algorithm are required. Among the soft decision codes, low density parity check codes (LDPC) can be a promising candidate for error correction in high density NAND flash memories due to their excellent error correction performance close to the Shannon limit. LDPC codes employed in NAND flash memories have large block lengths and very high code rate and should show good error correcting and error floor performance. Evaluating the error floor performance of these codes at very low frame error rates, typically around 10^−9 to 10^−10, require the use of high speed hardware simulators. Due to the reconfigurability and high speed, field programmable gate arrays (FPGAs) are largely used for evaluating the performance of LDPC codes. This thesis presents an FPGA based simulator system for evaluating the error correction and error floor performance of regular quasi cyclic (QC) LDPC Codes, for the application of large page size MLC NAND flash memories. Particularly, we targeted the algebraic QC-LDPC codes, which have high code rates and good error correcting and error floor performance. A generalized, high throughput and resource efficient hardware implementation of the QC-LDPC encoder and the decoder is given on FPGA. The proposed decoder can decode any regular QC-LDPC code including very high circulant weight QC-LDPC codes, such as euclidean geometry (EG) LDPC codes. The generalized and high throughput implementation of such large circulant weight QC-LDPC codes is not reported previously in the open literature. Moreover, the encoder and decoder hardware implementations are given on FPGA for very large page size (8 KB) of NAND flash memory, which are also not dealt previously in the open literature. A high speed and high quality floating point additive white Gaussian noise channel is implemented on FPGA using the high level synthesis method. The high level synthesis is used to rapidly prototype the channel on FPGA and to lower the development time of the LDPC simulator system. The very low consumption of the logic resources by the channel also enabled us to instantiate many channel modules in parallel, resulting in high throughput of the simulator. This thesis also presents the FPGA implementation and simulation results of two algebraic QC-LDPC codes for the page size 8 KB of NAND flash memory. Simulation results show good error correcting and error floor performance of the developed codes making them a promising candidate for error correction in NAND flash memories.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2595161
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