The widespread usage of NAND flashmemory technology has faced a surprising increment, far beyond what it was originally expected, mainly thanks to the advances in the manufacturing processes. Introducing for the first time in the literature the concept of the Service-Oriented Non VolatileMemories (SONVMs), the goal of this PhD thesis is to enhance the degree of runtime reconfigurability of an MLC NAND Flash controller, through the provision of userselectable differentiated memory access modes (i.e., services). Each mode implements a specific trade-off between read throughput, write throughput, reliability, and power. In particular, the proposed solution envisions adaptivity at two different layers: architectural level and device level. The architecture layer adaptivity is based on adaptive ECC decoding structure. It implements a Bose-Chaudhuri-Hocquenhem (BCH) ECC with programmable correction capability. The physical layer adaptivity is based on an adaptive high-voltage sub-system of the Flash memory device. After having considered the flexibility and the trade-offs in the physical layer and in the ECC sub-system in isolation, this thesis aims at acting upon their parameters at the same time to show unprecedented degrees of adaptivity to application requirements in the reliability/ performance/power optimization space, thus identifying a set of differentiated access modes that can be configured in the memory controller [
Service Oriented Non-Volatile Memories / Indaco, Marco. - (2014). [10.6092/polito/porto/2572951]
Service Oriented Non-Volatile Memories
INDACO, MARCO
2014
Abstract
The widespread usage of NAND flashmemory technology has faced a surprising increment, far beyond what it was originally expected, mainly thanks to the advances in the manufacturing processes. Introducing for the first time in the literature the concept of the Service-Oriented Non VolatileMemories (SONVMs), the goal of this PhD thesis is to enhance the degree of runtime reconfigurability of an MLC NAND Flash controller, through the provision of userselectable differentiated memory access modes (i.e., services). Each mode implements a specific trade-off between read throughput, write throughput, reliability, and power. In particular, the proposed solution envisions adaptivity at two different layers: architectural level and device level. The architecture layer adaptivity is based on adaptive ECC decoding structure. It implements a Bose-Chaudhuri-Hocquenhem (BCH) ECC with programmable correction capability. The physical layer adaptivity is based on an adaptive high-voltage sub-system of the Flash memory device. After having considered the flexibility and the trade-offs in the physical layer and in the ECC sub-system in isolation, this thesis aims at acting upon their parameters at the same time to show unprecedented degrees of adaptivity to application requirements in the reliability/ performance/power optimization space, thus identifying a set of differentiated access modes that can be configured in the memory controller [File | Dimensione | Formato | |
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PhD Thesis - Marco INDACO - part 1.pdf
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PhD Thesis - Marco INDACO - part 2.pdf
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https://hdl.handle.net/11583/2572951
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