CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems

As an answer to More Moore paradigm, Complementary Metal Oxide Semiconductor (CMOS) technology is continuously scaled to nanometer lengths and the silicon channel has reached its physical limit. It is time for the industry to explore novel material based devices that support future integrated circuits. Graphene is a two dimensional material which can be patterned through existing lithography process, therefore representing the most interesting material for concurrent, single-layer integration of devices and interconnects. Moreover, it shows unique mechanical properties alowing for the growth of new smart devices (e.g. wearable computing). In this dissertation, we focus on a novel device called as multi function reconfigurable gate proposed by IBM. This device consists of coplanar split gates underneath a large graphene sheet. A thin dielectric oxide layer separates the gates and the graphene sheet. Three metal-graphene contacts are present on top of the graphene sheet, called as front metal-graphene contacts. The co-planar gates dope the graphene electrostatically by using bipolar voltages. Here, we define logic ‘0’ as negative voltage (-Vdd/2) and logic ‘1’ (+Vdd/2) as positive voltage. The gates are connected to ‘0’ and ‘1’ making the graphene region above the gates p-type and n-type, respectively. The device do not rely on patterning the graphene sheet into nanoribbons. Advanced CMOS lithography techniques can be efficiently used for the gate patterning to achieve high density integration. Thus, this device is feasible for manufacturing and does not introduce any edge effects on the carriers. Using the above mentioned multi function reconfigurable gate, with appropriate terminal connections, a graphene 2:1 multiplexer is realized. An equivalent electrical model (also verilog-A model) is developed which is integrated with commercial SPICE simulators. With appropriate signals at the data inputs of the graphene 2:1 multiplexer, several other basic boolean logic gates (Inv, AND, OR etc) are realized. Some of these gates (like AND etc) have multiple architectures and a thorough comparison in terms of power and performance is presented. For the graphene reconfigurable gate based logic gates, we identify the possible timing arcs. The timing arc is defined from the input node to the output node. Only those input node which is responsible for a signal transition at the output terminal are considered. Two classes of timing arcs are identified, one from back gate terminals to output terminal termed as back-to-out transition, second from front contact terminal to the output terminal termed as front-to-out transition. An analytical model for delay and power for each of these timing arcs are presented and validated through SPICE simulator. The model validation is done for a range of input transition time and output load capacitance. The next step is to build integrated circuits with these graphene based gates. This is termed as synthesis and is present in the initial stage of the traditional IC design flow. There are various synthesis methods for designing conventional CMOS based circuits. These methods (namely Standard Cell Mapping (STC), Binary Decision Diagrams (BDD) and Look Up Table (LUT)) can be adopted for graphene RG based gates too. Various benchmark circuits implemented with these methods are characterized for power, area and performance. This helps designers in identifying the best implementation style for low power and high performance circuit. From testability perspective, the effect of various physical defects such as Short circuit between device terminals and open terminals on the graphene RG based logic gates is presented in this thesis. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, have been analyzed and mapped at a higher level of abstraction using proper fault models. Finally, in this thesis we propose ultra low power graphene logic gates, based on Adiabatic Computing. We design graphene pn-junction based adiabatic logic gates (INV/AND/OR) and are characterized for power and performance. A comparison between the graphene pn-junction based adiabatic logic gates and non adiabatic graphene logic gates is drawn and the adiabatic gates proved to have significant power savings.