A new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers. Instead of turning-off the buffers completely, a buffer portion is kept turned-on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade-offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalty.

Power-Gating Technique for Network-on-Chip Buffers / Casu, MARIO ROBERTO; Yadav, MANOJ KUMAR; Zamboni, Maurizio. - In: ELECTRONICS LETTERS. - ISSN 0013-5194. - STAMPA. - 49:23(2013), pp. 1438-1440. [10.1049/el.2013.3225]

Power-Gating Technique for Network-on-Chip Buffers

CASU, MARIO ROBERTO;YADAV, MANOJ KUMAR;ZAMBONI, Maurizio
2013

Abstract

A new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers. Instead of turning-off the buffers completely, a buffer portion is kept turned-on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade-offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalty.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2518587
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