We present a 0.007 mm2 impulse-radio ultrawide- band transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including radio frequency output buffers, consumes measured 30–45 pJ/pulse with a measured efficiency of ∼47% at 285 MHz center frequency and Vdd in the range of 0.97–1.17 V. At 1.2V supply, the 130 nm CMOS TX tolerates ±10% Vdd variation, maintaining robust lock and controlled power spectral density (PSD) at 300 MHz center frequency, −19 dBm radiated power at 1 MHz pulse-repetition frequency, and a fractional bandwidth of 0.23. At 300 MHz, the system achieves a measured 100 ps RMS jitter, and without output buffers, the sole PLL logic occupies an active silicon area of 0.0045 mm2.

A 130-nm CMOS 0.007 mm2 Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL / Marco, Crepaldi; Demarchi, Danilo. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - 60:5(2013), pp. 237-241. [10.1109/TCSII.2013.2251951]

A 130-nm CMOS 0.007 mm2 Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL

DEMARCHI, DANILO
2013

Abstract

We present a 0.007 mm2 impulse-radio ultrawide- band transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including radio frequency output buffers, consumes measured 30–45 pJ/pulse with a measured efficiency of ∼47% at 285 MHz center frequency and Vdd in the range of 0.97–1.17 V. At 1.2V supply, the 130 nm CMOS TX tolerates ±10% Vdd variation, maintaining robust lock and controlled power spectral density (PSD) at 300 MHz center frequency, −19 dBm radiated power at 1 MHz pulse-repetition frequency, and a fractional bandwidth of 0.23. At 300 MHz, the system achieves a measured 100 ps RMS jitter, and without output buffers, the sole PLL logic occupies an active silicon area of 0.0045 mm2.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2508084
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