Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.
Flexible LDPC Decoder Architectures / M. Awais; C. Condo. - In: VLSI DESIGN. - ISSN 1065-514X. - STAMPA. - 2012(2012), pp. 1-16. [10.1155/2012/730835]
|Titolo:||Flexible LDPC Decoder Architectures|
|Data di pubblicazione:||2012|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1155/2012/730835|
|Appare nelle tipologie:||1.1 Articolo in rivista|