SAT--based Unbounded Model Checking based on Craig Interpolants is often able to overcome BDDs and other SAT--based techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact circuit representations of state sets, as they abstract away several nonrelevant details of the proofs. We propose three main contributions, aimed at controlling interpolant size and traversal depth. First of all, we introduce interpolant--based dynamic abstraction to reduce the support of computed interpolants. Subsequently, we propose new advances in interpolant compaction by redundancy removal. Finally, we introduce interpolant computation exploiting circuit quantification, instead of SAT refutation proofs. These techniques heavily rely on an effective application of the incremental SAT paradigm. The experimental results proposed in this paper are specifically oriented to prove properties, rather than disproving them, i.e., they target complete verification instead of simply hunting bugs. They show how this methodology is able to stretch the applicability of interpolant--based Model Checking to larger and deeper verification instances.
Boosting Interpolation with Dynamic Localized Abstraction and Redundancy Removal / CABODI G; M. MURCIANO; NOCCO S.; S. QUER. - In: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. - ISSN 1084-4309. - 13:1(2008).
|Titolo:||Boosting Interpolation with Dynamic Localized Abstraction and Redundancy Removal|
|Data di pubblicazione:||2008|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1145/1297666.1297669|
|Appare nelle tipologie:||1.1 Articolo in rivista|